Optimal Selection of Supply Voltages and Level Conversions During Low Power Data Path Scheduling

In t'his paper we will consider how to select an optimal set of supply voltages and account for level conversion costs when optimizing the schedule of a resource domina.ted data path for minimum average power dissipation. Integer linear program (ILP) and non-linear program (NLP) formulations are presented for a minimum power schedule under latency and throughput constraints. Results are presented for several data path topologies under minimum latency constraints and under more relaxed latency constraints. The optimization demonstrated substantial benefit going from one to two supply voltages, but minimal additi,onal benefit from any additional supplies. For example, a Kalman filter benchmark produced a power estimate of 356.7mW for a single 5V supply, 265.4mW for 4V and 5V supplies, but no additional improvement for three supplies. Increasing minimum schedule latency by 50% improved optimization results substantially for two and three supply voltages but in mod cases there was no improvement at all for a single optimal supply voltage. 'This research was supported in part by ARPA (under contract F33615-95-C-1625) A great deal of current research is motivated by the need for decreased power dissipation while satisfying requirements for increased computing capacity. In portable systems, battery life is a primary constraint on power. However, even in non-portable systems ;such as scientific workstirtions, power is still a serious constraint due to limits on heat dissipat;ion. One: design technique that promises substantial power reduction is voltage scaling. The term "voltage scaling" refers to the trade-off of supply voltage against circu:it area and other CMOS device parameters to achieve reduced power dissipation while maintaining circuit performance. The dominant source of power dissipation in a conventional CMOS circuit is due to the cha.rging and and discharging of circuit capacitances during switching. E'or static CMOS, switching power is proportional to V . [15]. This relationship provides a st.rong incentive to lower supply voltage, especially since changes to any other design parameter can only achieve linear savings with respect t o the parameter change. The penalty of voltage reduction is a loss of circuit performance. The propagation delay of CMOS is proportional t;o [15], where 'VT is the transistor threshold voltage. A variety of techniques are applied to compensate for the loss of performance with respect to Vdd including reduction of threshold voltages, increasing transistor widths, optimizing the device technology for a lower supply voltage, and shortening critical paths in the data path by means of parallel architectures and pipelining. Chandrakasan et. al. describe: these techniques in [lfi]. Dais path designs can benefit from voltage scaling even without changes in device technol* gies. Algorithm transformations and scheduling techniques can be used to increase the latency available for some or all data path operations. The increased latency allows an operation to execute a t a lower supply voltage without violating schedule constraints. " Architecture-Driven Voltage Scaling" is a name Chandrakasan et. al. applied to this approach. A number of researchers have developed systems or proposed methods that incorporate architecture driven voltage scaling [4, 6, 7, 11, 5, 8, 91. The HYPER-LP system [4] is a system that applies transformations to the data flow graph of an algorithm to optimize it for low power. Other systems accept the algorithm as given and apply a variety of riechniques during scheduling, module selection, resource binding, etc. to minimize power dissipation. All of the syatems mentioned above try to exploit parallelism in the algorithm to shorten critical paths r;o that reduced supply voltages can be used. Most of the systems [4, 6, 7, 11, 51 try to also minimize switched capacitance in the data path. Raje and Sarrafzadeh [9] take switching activities as given. They schedule the data path and assign voltages to data path operators so as t o minimize power given a predetermined set of supply voltages. Th'e objective of this research has been to incorporate multiple supply voltage selection and level conversion costs into the low power optimization of resource dominated data paths. In this paper, ILP and NLP formulations are presented that generate a schedule with supply voltages assigned to each operation so as to minimize average power dissipation. These formulations are designed for resource dominated data paths for which area, performance, and power dissipation are dominated by the data path resources (arithmetic operators and registers). For the remainder of this paper, we will refer to our ILP formulation as MPSVS (Minirnum Power Schedule with Voltage Selection). MPSVS is closest in scope to the work of Raje and Sarrafzadeh [9]. However, MPSVS is distinguished by the fact that it selects an optimal set of one, two, or three supply voltages from a larger set of possible supply voltages, and factors level conversion effects into the delay constraints and power estimate. The NLP formula.tion generates a schedule with continuous valued schedule times and iunlimited supply voltager. The NLP solutions are included for comparison to ILP results. 2 I:LP Model for Minimum Power Sched.ule With Voltage Select ion The MPSVS formulation describes a minimum power scheduling problem under latency and multiplle supply voltage constraints. It is a zero-one integer linear program ILP similar in structu1:e to data path scheduling formulations described by DeMicheli [14] a'nd Gebotys [lo]. The primary input to MPSVS is a data flow graph that specifies the ~perat~ions, data flows, and latlency constraints for a data path. Other inputs to MPSVS include: :;pecification of a discrete set of permitted supply voltages, a limit on the number of supply voltages that can be selected, a minimum difference between voltages that can be selected, average switching activities for each data path operation, and nominal propagation delay and average energy dissipation values for each data path resource. Solution of the minimum power scheduling problem results in a data path schedule, selection of an optimal set of supply voltages, and assignment of a supply voltage to each operation. MPlSVS makes the following assumptions: a one-to-one relationship of operator types to modi~le types, unlimited resources, and a predetermined clock period. Furtberrnore, the outputs of all operations are registered for an entire sample interval of the data path. Level converters, when needed, are always located at the inputs to an operator. Delay and power dissipation are accounted for arithmetic operations, rel:isters, and logic level conversions. Worst case propagation delay and average energy dissipation per input switching event were measured for each type of operator and register under nominal operating conditions. MPSVS re-scales the delay and energy estimates to be consist,ent with the supply voltages, switching activities, and estimated load capacitances in the data path. Energy estimates for operators and registers are scaled as E = Eo x q, where Vo is the nominal supply vo voltage, V is the actual voltage, and Eo is the nominal energy. Delay estimates for operators jw, where tpo is the nominal propagation delay and and registers scale as t p = t f l x x vVT VT is tlne MOS transistor threshold voltage. Delay and energy estimates for level converters are treated in a similar manner except that they are functions of two supp1;y voltages rather than one. Details of the level conversion models are given in section 4.1. In all cases delay is scaled linearly with respect to load capacitance. Energy is scaled linearly with respect to both load capacitance and switching activity. The objective function for MPSVS is an estimate of data path power dissipation as a function of supply voltages and the rate at which data samples are processed. The average energy of each data path operation, register operation, and level conversion is determined based on the .voltage assignments. The sum of these energies over the entire data pa.th represents the average energy dissipated by a single execution of the data path. The total energy is divided by the time interval between data samples to calculate average power.